Development

VeriSim

senolgulgonul.github.io ↗

Verilog simulator built by compiling Icarus Verilog to WebAssembly. No server, no install: edit, compile, simulate, view waveforms, and synthesize to a gate-level or RTL schematic

Category

Development

License

GPL-2.0

Stars

★ 20

Added

2026-06-20

• simulate
• verilog
• schematic